FIG. 1 is a timing chart 2 illustrating a typical high-speed data signal in which the clock signal is intrinsic to the data signal. Here, five data bits are shown, representing the sequential binary sequence {10010}.
In at least one currently employed clock recovery circuit, a data signal is oversampled by a factor of two to recover the “edge” between two data bits and adjust the phase of the recovered clock based on this edge measurement.
For example, FIG. 2 shows the same timing chart 2 as FIG. 1, and further illustrates the ideal data sample points 4 and edge sample points 5 used by a factor-of-two oversampling clock recovery circuit.
FIGS. 3A and 3B illustrate how an edge between two data bits is recovered. In FIG. 3A, the two data samples 8,10 have different values, so it is clear that an edge occurred between them. Here, because the edge sample 9 has the same value as the first data sample 8, it is deduced that the sample 9 was early, i.e. the sample occurred prior to the actual edge between the two bits. With the knowledge that the edge was sampled early, the sampling clock can be adjusted by adding a small delay.
In FIG. 3B, again the two data samples 8, 10 have different values, so again it is clear that an edge occurred between them. Now, because the edge sample 9 has the same value as the second data sample 10, it is deduced that the sample 9 was late, i.e. the sample occurred after the actual edge between the two bits. With the knowledge that the edge was sampled late, the sampling clock can be advanced.
Of course, where the value does not change between two consecutive data bits, as with the two consecutive 0s in FIG. 1, no edge exists to aid in clock recovery.
FIG. 4 is a block diagram of a clock recovery loop 20. This loop 20 is basically a two stage counter that accumulates the net difference between early and late edges detected by a set of samplers 22, four for example. For each bclk cycle, the samplers 22 acquire four equally spaced values from the line, i.e. two data bit samples and the edges immediately following these bits, clocked by a four-phase clock from a phase interpolator 24.
The early/late logic 26 examines these four samples, along with the previous (historical) data bit, and determines whether one or more edges occurred and whether the sample points are unambiguously early or late with respect to the data signal edges. (Early and late here refers to early and late samples. This is exactly the opposite of an early or late edge. That is, an early sample corresponds to a late edge.)
The early/late logic 26 provides early and late indications accordingly. These indications become inputs to the two-stage counter 28, 29. The first stage 28 of the counter divides by N, four for example, to filter the number of noisy edge samples, i.e., the number of early/late indications. The second stage 29 of the counter has 2P counts, corresponding to P phase steps per bit cell over the two bit cells spanned by the half-bit-rate bclk. In this figure, there are P=32 phase steps per bit cell and thus the counter has 2P=64 states encoded as a 6-bit phase setting.
Thus, overall, the two-stage counter 28, 29 forms a divide by 2×P×N counter that accumulates the net difference between the number of early and late samples. The divide-by-N counter 28 acts to filter the early and late signals, reducing the variance due to jitter on the input signal. The divide-by-2P phase counter 29 accumulates the net early and late signals out of the divide-by-N counter to generate a log2(2P)=6 bit phase setting signal.
The phase interpolator 24 accepts a reference clock, bclk, and the phase setting output 25 from the divide by 2P counter 29. The phase interpolator 24 generates a sample clock 27 for each of the four samplers 22. The sample clock for the first sampler is displaced from the reference clock by an amount determined by the phase setting from the divide by 2P counter. The relative phase from the reference clock to the first sampler clock is 360×p/64 degrees, where p is the phase setting output 25 from the counter 29. For example, if p=0, the two clocks are exactly aligned; and if p=16, the first sample clock is displaced by 90 degrees from the reference clock. The four sample clocks are spaced evenly around the unit circle—each following the previous clock by 90 degrees.
FIG. 5 is a timing chart illustrating operation of the phase interpolator 24 of FIG. 4. The reference clock (blck) pulse is shown at 60, while 61 and 62 each illustrates the four outputs of the phase interpolator 24 where p=0 and p=8, respectively.